Design For Testability

Design For Testability (DFT) refers to those design practices that assist designers to reduce cost of test pattern generation, enhance fault coverage, and hence reduce defect levels at mass production.

GUC DFT methodology provides a complete solution including RAM BIST, ROM BIST, at-speed RAM BIST, regular scan, AC scan, scan compression, boundary scan (JTAG), and ATPG, to achieve ultra-high test coverage.

Advanced DFT Solution

 

Success Story

Process Gate Count Application DFT Feature
7FF 3.4B HPC

DC/AC Scan, HBM interposer test, MBIST, Fail core identification, IEEE 1149.1/1149.6

7FF 2.75B Networking

DC/AC Scan, Fair core testing for logic redunduncy, MBIST, TCAMBIST

12FFC 1.25B AI

DC/AC Scan, ultra-scan, @speed MBIST, SRAM repair

12FFC 220M Camera

DC/AC Scan for 800+ clock domains, @speed MBIST

16FFGL+ 1B HPC

DC/AC Scan,  HBM interpoer test, @speed MBIST, SRAM repair

16FFLL+ 20.1M AI DC/AC Scan, @speed MBIST, System BIST, IEEE 1149.1/1149.6
28HPC+ 71M Networking

DC/AC Scan, @speed MBIST, System BIST, SRAM hard/soft repair

28HPC+ 407M AI

DC/AC Scan solution for 350+ tiles, Scan Compress, One chain for diagnosis, @speed MBIST

28HPC 240M Networking

DC/AC Scan, @speed MBIST, SerDes AC Scan, IEEE 1149.1, eFuse Test

28HPC 15M SSD

DC/AC Scan, MBIST,  DDR3/ PCIe-G3/ ONFi/ eFuse

28HPM 100M SSD DC/AC Scan, MBIST, IEEE 1149.1, PCIe/ DDR loopback, Thermal sensor test
28HPM 20M WiGig DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1, PCIe loopback test, AFE loopback test, Thermal sensor test
28HPM 50M DSC Application DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1, PCIe loopback, DDR loopback
40LP 20M Cellular BB DC/AC Scan, MBIST, IEEE 1149.1, Power switch test, USB/ eFuse/ Codec/ ADC Test
40G 60M LTE Baseband DC/DC/AC Scan, MBIST, IEEE 1149.1, SRAM repair
40EP 10M Display DC/AC Scan, MBIST, IEEE 1149.1, eDRAM repair