Package Service

GUC packaging service provides product package evaluation, package design, substrate layout and complete electrical and thermal simulation to ensure product can meet system performance specification.


Package Design

Delivered 2.5D IC design, and released 122 LAN 28G SerDes package solution and Coreless substrate into mass production


 Package Simulation

  • Chip-Package-Board co-design and co-simulation are critical to high speed products for performance enhancement by optimizing floor plan, layout, pad location, I/O and electrical timing budgeting among chip, package and board. GUC’s co-simulation includes mechanical, electrical signal integrity and power integrity and thermal performance.
  • Achieve cost effectiveness by identifying optimized package configuration and size and substrate layers.



SiP (System-in-Package)

  • GUC’s SiP capability and experience bring customers the benefits of product miniaturization, better noise/power consumption/EMI performance and integration of heterogeneous and mixed process technologies.
  • Combine with SoC and KGD total test solution for high manufacturing yield and quality.




Success Cases

Application Integrated with SoCPackageSize (mmxmm)
Camera LPDDR3 PoP  14 x 14
Processor PCIE PHY MCMTFBGA  23 x 23
Network USB, SDRAM MCMTFBGA  10 x 10
Camera FCRAM x2 SNWLFBGA 15 x 15
Codec MDDR x2 SNWFBGA 15 x 15
Camcorder MDDR S2TFBGA 7.5 x 5.0
Ethernet Switch LPDDR2 STKFC LFBGA 8 x 8
Digital Camera LPDDR2 STKFC VFBGA 6.5 x 6.5
Car Camera SDRAM, Rx, Tx LFBGA 14 x 14
Automotive MEMS, ROIC LGA 3 x 3
MCU Flash EP-LQFP 14 x 14
Solar Energy SRAM LQFP 10 x 10
MCU NOR Flash QFN 12 x 12
RFID Flash QFN 7 x 7


2.5D IC Packaging

  1. 2.5D IC packaging technology integrates multiple chips into one package using a sub-micron process silicon interposer. It enables product higher performance, lower power consumption and smaller form factor by the short chip-to-chip distance and high routing density on interposer. It also supports advanced technology node Si yield and cost saving via die partitioning and multi-core expansion.



  • GUC’s 1st 2.5D IC integrated GUC’s SoC, interposer and package designs and HBM2 chip by TSMC CoWoS process. It successfully validated GUC’s HBM IP, interposer design, 2.5D IC DFT, package and test solutions and enables GUC’s multiple 16nm FinFET 2.5D ASICs design.