Chip Implementation Methodology

GUC integrates commercial EDA and in-house solution to make sure design quality and efficiency

• Code purification and coverage analysis
• Topographic Synthesis
• DFT integration platform to support HPC multi-core design
• Low power and IR prevent DFT
• IP integration/IP quality checking methodology
• Multi-level hierarchical design and implementation methodology for HPC multi-billion gate design
• Hierarchical timing signoff for HPC multi-billion gate design
• PowerMagic® low power methodology
• High-speed IP testing methodology
• 2.5D Interposer methodology with CoWoS and Die to Die methodology
• One Pass Implementation platform
• Dynamic IR, SI and timing aware implementation
• OCV (On Chip Variation) analysis and prevention methodology