ASIC Service

GUC has been delivering SoC design services on 0.5um to 3nm technology. GUC chip implementation solution resolves the challenges of multi-billion gates design, GHz operating frequency, noise coupling at deep submicron, IR drop, ESD, design for manufacturing (DFM), and time to market requirements.

In addition to hierarchical physical synthesis, clock tree synthesis, static timing analysis with on chip variation (OCV), formal verification, multiple power domain/on-off domain verification, cross-talk fixing and prevention, and LVS/DRC, GUC's advanced design flow, equipped with quick prototyping, automatic power design solution (power plan with IR & routability aware, power switch stitching for rush current and ramp-up time budget, power density checker for dynamic IR prevention), iterations reduction timing driven solution (Sign off customization for different PVT, stage base OCV (SBOCV), data flow analyzer, clock adjust cell (CAC), Hold free cell) has been proven in hundreds of customers' first silicon successes at deep submicron technology.

On the other hand, GUC also delivers comprehensive design-for-testability (DFT) services including scan insertion, boundary scan, memory BIST with smart BIST grouping, memory repair, memory ECC solution, scan re-ordering, scan-ECO, low power test pattern generation and HPC-driven DFT services.

Besides, GUC provides IP hardening, IP test circuit/test pattern integration, SoC integration service from spec to GDSII or RTL to GDSII. GUC has successfully integrated complicated SoC and produced them in volume for hundreds of customer projects throughout the years.