GUC’s multi-die interLink (GLink-2.5D/-3D) and UCIe IP provide the world’s best-in-class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a package for applications such as High Performance Computing, Data Center, Artificial Intelligence and Networking.
GLink-2.5D IP utilizes single-ended signaling on parallel bus with DDR clock forwarding. This allows for up to 8/16Gbps per pin, consuming only 0.25pJ/bit on TSMC’s RDL-based InFO (Integrated-Fan-Out) or CoWoS (Chip-on-Wafer-on-Substrate). One slice has 32 full-duplex lanes, and one PHY has 8 slices with a maximum bandwidth of 2/4Tbps. For the most advanced GLink version, one slice will have 56 full-duplex lanes, and one PHY has 8 slices with a maximum bandwidth of 7.5Tbps.
GUC leverages its multi-year, multi-generation GLink-2.5D experience to the development of UCIe IP. GUC’s UCIe IP follows the UCIe standard to provide industry-leading, 32G per lane die-to-die inter connect, achieving the best beachfront efficiency of 5+ Tbps/mm in full duplex.
The GLink-3D IP family provides a high-speed die-on-die interface with Master PHY and Slave PHY. They are used to transmit data between dies, assembled using TSMC’s System on Integrated Chips (SoIC) 3D stacking technology (3DFabric). The IP supports both Wafer-on-wafer (WoW) and Chip-on-wafer (CoW) assembly, with both face-to-face and face-to-back options. Both Master and Slave PHY are built with TX and RX Data and Command Slices in a modular way. Each Data Slice allows transferring 16 bits at 5.0 Gbps in one direction, totaling 80 Gbps per Data Slice.
- GLink
- Best PPA PHY and Controller
- Sub-system integration
- Bring up guideline
- DFT guideline
- GUC patterned routing
- GUC Verification flow
- IR co-design flow
- D2D DFT
- SoC-interposer substrate PCB co-design
- System level co-design
- Verification flow
- PKG Design
- Qualification item, hardware and execution
- Characterization, yield, DOE