日期 標題
110/10/18 GUC's Spec-in Capability Enabled 1st Silicon Success of Lidar Application
110/10/18 GUC Proprietary Interposer Design to Achieve 7.2Gbps, Enable HBM3 for Hyperscale HPC / AI / Networking SoCs
110/10/18 GUC Taped out Industry-leading 5Tbps / mm, 5nm Die-to-Die GLink 2.3 IP
110/09/22 Low Power DFT by Scan Capture Power - ICG (isolation clock gating) insertion to improve production test efficiency
110/09/20 GUC N5 HBM2E 3.6G/4G Silicon Proven
110/09/20 GLink-3D IP has been taped out in Apr'21 using TSMC 3DFabric Technology and granted by the U.S. patent in Jun'21
110/08/17 Scan Shift Power – Q Gating: Over 20% IR improvement in production
110/08/16 GUC Leads the Market to Provide CoWoS-R RDL Interposer Design Service and Verify on HBM2E 4G
110/07/19 GUC Low Voltage Re-characterization Service to Optimize the Low Power Design and SoC PPA in Early Design Phase
110/07/19 GUC Provides InFO_oS Packaging Service for AI/HPC/Networking Applications
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