GUC multi-die interLink (GLink-2.5D/-3D) IP provides world’s best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a package for applications such as High Performance Computing, Data Center, Artificial Intelligence and Networking.
The GLink-2.5D IP utilizes single-ended signaling on parallel bus with DDR clock forwarding. This allows for up to 8/16Gbps per pin consuming only 0.25pJ/bit on TSMC’s RDL-based InFO (Integrated-Fan-Out) or CoWoS (Chip-on-Wafer-on-Substrate). One slice has 32 full-duplex lanes and one PHY has 8 slices with 2/4Tbps maximum bandwidth. For the next generation GLink, one slice will have 56 full-duplex lanes and one PHY has 8 slices with 7.5 Tbps maximum bandwidth.
The GLink-3D IP family provides high speed die-on-die interface Master PHY and Slave PHY. They are used to transmit data between dies, assembled using TSMC System on Integrated Chips (SoIC) 3D stacking technology (3DFabric). The IP supports both Wafer-on-wafer (WoW) and Chip-on-wafer (CoW) assembly, both face to face and face to back options. They are used to communicate between Master and Slave PHY. Both Master and Slave PHY are built of TX and RX Data and Command Slices in a modular way. Each Data Slice allows transferring 16 bits at 5.0 Gbps to one direction, totally 80 Gbps per Data Slice.
- GLink
- Best PPA PHY and Controller
- Sub-system integration
- Bring up guideline
- DFT guideline
- GUC patterned routing
- GUC Verification flow
- IR co-design flow
- D2D DFT
- SoC-interposer substrate PCB co-design
- System level co-design
- Verification flow
- PKG Design
- Qualification item, hardware and execution
- Characterization, yield, DOE