Low Power DFT by Scan Capture Power - ICG (isolation clock gating) insertion to improve production test efficiency
Challenge: Scan patterns may have higher capture toggle than function mode
Solution: ATPG (Automatic Test Pattern Generation) to achieve test coverage effectively by high toggle capture behavior
Benefit of Add-on ICG
- Case A: Reduce >60% capture toggle under similar test coverage and pattern efficiency
- Case B: Achieve >10% better test coverage for lower capture toggle constraint
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