HPC, AI and Networking technique is used for many applications such as data center computing, edge computing, connectivity network etc.. The built-in repeated computing engine and memory bandwidth is more as possible to enlarge the computing capability, so the design complexity and chip size are increase more at HPC/AI/Networking era. Traditional design flow has bottleneck to serve this complexity design. GUC has state-of-art solutions including multi-level hierarchical design, hierarchical timing sign-off, high power IR prevention DFT, high-speed IP integration, 2.5D package(CoWoS/InFO) design within HBM/D2D IP subsystem and chip-package system PI/SI verification to ensure customer design success. With this total solution, GUC had success taped out many flagship SoC design.

Comprehensive Solution for Flagship SoC Design

  • Low Power

    • MTCMOS, multi-bit FF, MSV, DVFS for power reduction
    • Customize sign off condition for different PVT
    • Shifted clocks distribution for current peaks spreading
    • Low Voltage for power efficiency optimization
    • Low Power Cell Customization / PowerHERO
  • 2.5/3D

    • CoWoS interposer with 4 HBM2E(3.2GHz) /HBM3 (7.2GHz)
    • 2.5D CoWoS /D2D/DonD IR/PI/SI
    • D2D with G-link-fs (8-12 GHz) IP
    • SoIC DonD with GLink-3D IP
  • DFT

    • IR-power aware DFT plan, Smart memory BIST grouping
    • Faulty core / tile identification
    • In-house Scan-ECO
    • High-speed interface IP / 2.5D / 3D testing integration
  • Physical Design

    • Automatic power plan creation with IR & routing resource aware
    • CTS : clock adjust cell, big driving clock buffer, H-tree, clock mesh
    • Multiple-Billion gate design with Multiple SerDes integration
    • Distributed Clock Useful Skew to Reduce Peak Current
  • Design integrity

    • Performance monitor kit
    • Hybrid STA with in-house optimal hyper-scale model
    • Ramp up current analysis / Co-sim with L/B, Probe Card, Package, PCB
    • Aging / Jitter effect simulation


Process Gate Count Application Key Feature
7nm >3B HPC CoWoS with 4 HBM, Fail core identification, Hyper Scale Hier. STA, H-tree CTS
2-level Hier. design, IR-aware DFT, channel-less design
7nm >3B Networking Fail core identification for redundancy, H-tree, 112G SerDes integration, 2-level Hier. design, IR-awar
12nm 1.25B AI SRAM repair, IR-aware DFT, 2-level Hier. design, multi-core IR ramp-up analysis
16nm 1B HPC CoWoS with 4 HBM, IR-aware DFT, 2-level Hier. design
16nm 1.6B AI Fail core identification, IR-aware DFT, Hyper Scale Hier. STA, fishbone clock, channel-less design
28nm 407M AI IR-aware DFT, H-tree CTS, shift clock distribution for peak power reduction
28nm 240M Networking SerDes integration, Chip-package PI/SI