创意聚焦

GUC has successfully taped out N5 HBM3 8.4G test chip and expected to be silicon validated in 4Q22

GUC HBM Record and Roadmap

• N5/N7 HBM3 IP available
• N3 HBM3 IP to be available in 2H22
• Support both CoWoS-S and CoWoS-R
• Multiple HBM2/2E customer AI/HPC products under mass production
• Multiple HBM3 customer AI/HPC/Networking products are in design stage

GUC HBM/CoWoS Total Solution

• In-house HBM2E/HBM3 Controller and PHY IP

• Proprietary interposer layout pattern to achieve best SI/PI

• Support Y direction offset by zig-zag or 45o

• Embedded all-pin, in-mission mode performance and health monitoring by proteanTecs

• Best CoWoS production management