GUC built up TSMC N3 design flow and completed silicon correlation in 2021, migrating to N3E technology in 2022

  • GUC built up N3 design flow from RTL to GDSII and developed GUC design methodology to overcome N3 design challenge (hybrid row design, routing, IR mitigation…etc.)
  • A comprehensive test chip design and silicon correlation with SPICE simulation result, including: 
    • CE (Computing Engine): 143M Stdcell, nominal voltage 0.75V
    • Customized low power cells: XOR, XNOR, ADDER and MBFF for customers’ low power design
    • CPM (Chip Performance Monitor): Project silicon correlation and debugging 
  • Developing N3E design flow, plan to IP (GLink 2.3LL & HBM3) tape-out in 2H22

GUC 核心优势

  • Advanced Packaging Technology Leadership
  • Design Engineering Excellence
  • Customer Trusted Service