Design For Testability (DFT) refers to those design practices that assist designers to reduce cost of test pattern generation, enhance fault coverage, and hence reduce defect levels at mass production.
GUC DFT methodology provides a complete solution including RAM/ROM BIST, DC/AC Scan, Logic BIST, ATPG and boundary scan (JTAG), to achieve ultra-high test coverage.

Advanced DFT Solution

Target Methodology Implementation Approach
Low DPPM Scan test Fault detection : Stuck-at, Transition delay, Small delay fault, Path-delay fault, Static/Dynamic bridge fault, Cell aware fault
Memory BIST At-speed test, diagnosis, Data retention test
JTAG test IEEE 1149.1 / 1149.6,
IO DC test
IP integration test IP BIST test, CoWoS interposer testing for HBM… ect.
Cost Reduction Test pattern reduction Scan compression,
ATE Xn mode & memory pooling
On-chip clock controller Utilize low-end tester
Low pin-count test Serializer solution for small package
Yield Improvement Power-aware DFT Power-aware scan clock planning,
Smart SRAM BIST grouping
CDA, Q-gating, ICG-gating, Low power ATPG
Memory Repair, Fail core classified SRAM solution, EDRAM solution, Fail core identification for AI-HPC
Functional Safety In-System Test System Logic BIST, System Memory BIST

Success Story

Process Gate Count Key features DFT Feature
7nm >3B HPC DC/AC Scan, HBM interposer test, MBIST, IEEE 1149.1/1149.6, Fail core identification
7nm >3B Networking DC/AC Scan, Fail core testing for logic redundancy, MBIST, TCAMBIST
12nm 1.25B AI DC/AC Scan, Ultra-scan, @speed MBIST, SRAM repair
12nm 220M Camera DC/AC Scan for 800+ clock domains, @speed MBIST
12nm 147M Drone DC/AC Scan, @speed MBIST, IEEE 1149.1/1149.6
12nm 22M Storage DC/AC Scan, @speed MBIST, IEEE 1149.1/1149.6, Thermal sensor test
12nm 340M 5G DEF DC/AC Scan, Scan Compress, Ultra-scan, @speed MBIST, IEEE 1149.1/1149.6, AFE loopback, Thermal sensor test
16nm 1B HPC DC/AC Scan, HBM interposer test, @speed MBIST, SRAM repair
16nm 20.1M AI DC/AC Scan, @speed MBIST, System BIST, IEEE 1149.1/1149.6
16nm 14M Automotive DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1/1149.6, System BIST
28nm 71M Networking DC/AC Scan, @speed MBIST, System BIST,SRAM hard/soft repair
28nm 100M SSD DC/AC Scan, MBIST, IEEE 1149.1, PCIe/ DDR loopback, Thermal sensor test
28nm 20M WiGig DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1, PCIe loopback, AFE loopback, Thermal sensor test
40nm 20M Cellular B DC/AC Scan, MBIST, IEEE 1149.1, Power switch test, USB/ eFuse/ Codec/ ADC
40nm 60M LTE Baseband DC/DC/AC Scan, MBIST, IEEE 1149.1, SRAM repair
40nm 10M Display DC/AC Scan, MBIST, IEEE 1149.1, eDRAM repair