Speed Up Your SoC Time-to-Market
Speed up your SoC time-to-market with GUC design automation tool and flow. Design quality is 100% guaranteed!
Key Features
- Automatically generate integrated RTL and testbench for SoC
- Support CHI/ACE/AXI/AHB/APB system buses
- Support 27 types of register files
- Support memory wrapper
- Support ATE mode
Key Benefits
- Automatically generate design and documents from spec
- Specs equal design. Correctness is 100% guaranteed
- Speed up SoC time to market
Function and ATE Design Generation Flow
Case Study: A 20M+ Gate SoC
A 20M+ Gate SoC
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~200 Instance/Master/Slave counts
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Large NIC BUS Matrix (31x91)
Shorten design and verification turn-around time
- 1st round from months to few days
- Iterations from weeks to < 1 day
- Auto-gen RTL and testbench. Fully verified
- Auto-gen design documents. Fully aligned with design
GUC 核心優勢
- Advanced Packaging Technology Leadership
- Design Engineering Excellence
- Customer Trusted Service