GUC early adopts TSMC's most leading N3 technology, in-house design flow and IP will be completed by silicon correlation
- GUC worked with EDA vendors to build up N3 design flow from RTL to GDSII, and completed N3 key design elements
- CE (Computing Engine): 143M Stdcell, nominal voltage 0.75V
- Customized low power cells: XOR, XNOR, ADDER for customers’ low power design
- CPM (Chip Performance Monitor): Project silicon correlation and debugging
- Start to cooperate N3 flow and design for customers' test chips
GUC 核心優勢
- Advanced Packaging Technology Leadership
- Design Engineering Excellence
- Customer Trusted Service