創意聚焦

• High performance, small area TCAM compiler solution from N16 to N4P
• 15% faster cycle time and 6% smaller area
  • Different Vt flavors for speed and power trade-off
  • Word bank and bit bank options for optimal area and speed target
• 1st cut success in N7 and N12 TK customer chips, go for MP smoothly

Sub Title

1. Challenge: Huge design STA long run time & machine memory usage Challenge: Huge design STA long run time & machine memory usage Challenge: Huge design STA long run time & machine memory usage
2. Solution: GUC hybrid STA methodology for huge design
3. GUC hybrid model: optimized model + feedthrougth model
4. Real case example : improve block model reduction rate to over 90% and shorten timing closure TAT to 10~30%
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