GUC Announces a New Performance Monitor Methodology and Solution, Published on IEEE
Title: A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical Paths
Published in: 2021 58th ACM/IEEE Design Automation Conference (DAC)
Date of Conference: 5-9 Dec. 2021
Date Added to IEEE Xplore: 13 November 2021
DOI: 10.1109/DAC18074.2021.9586155
Publisher: IEEE
Abstract: Monitoring system-on-chip performance under process, voltage, and temperature (PVT) variations is very challenging, especially when the parasitic effects dominate the whole chip performance in advanced process nodes. Most of the previous works presented the performance monitoring methodologies based on known/predicted candidates of critical paths under different operating conditions. However, those methodologies may fail when the critical path is misrecognized or mispredicted. This paper proposes a novel machine-learning based chip performance monitoring methodology to accurately match the chip performance without requiring the information of critical paths under various PVT conditions. The experimental results based on measured chip performance show that the proposed methodology can achieve 98.5% accuracy in the worst case under wide-range PVT variations.
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