Date
Title
Sep. 20, 2022
GUC Industry-leading 5Tbps/mm Die-to-Die GLink 2.3LL IP Showing Good Silicon Results
Sep. 07, 2022
TSMC 2022 Technology Symposium Recap
Aug. 17, 2022
Power Aware Scan Structure Planner
Jul. 20, 2022
GUC New Automation Methodology Improves 60~80% TAT for Complex SoC Design
Jul. 13, 2022
Explore GUC 2022 Solution Flyers
Jul. 13, 2022
GUC Presents the 2D/2.5D/3D Chiplets and Interface Standardization at 2022 WSCE (Nanjing, China)
Jun. 08, 2022
GUC Announces to Join UCIe as Contributor Member
Jun. 07, 2022
GUC Will Be Exhibiting at TSMC 2022 Technology Symposium
May. 26, 2022
GUC Proprietary Interposer Design to Achieve 8.4Gbps, Enable HBM3 for Hyperscale HPC / AI / Networking SoCs
May. 20, 2022
GUC GLink 2.5D and 3D Presentation to OCP/ODSA Committee
May. 18, 2022
GUC HBM3 Platform is Silicon Proven at TSMC N7 and CoWoS Technology
Apr. 27, 2022
GUC Joins Universal Chiplet Interconnect Express (UCIe) as Contributor Member
Apr. 21, 2022
GUC to Present at ChipEx 2022
Mar. 22, 2022
GUC Has Successfully Taped Out N5 HBM3 8.4G Test Chip
Feb. 21, 2022
GUC Completed TSMC N5 V1.2 Enhancement, Offering New Design Flow to Close S2S Gap and Yield Improvement
Jan. 18, 2022
GUC built up TSMC N3 design flow and completed silicon correlation in 2021, migrating to N3E technology in 2022
Jan. 17, 2022
GUC Validates TSMC CoWoS-R® Design Solution using N5 4Gbps HBM2E