GUC New Automation Methodology Improves 60~80% TAT for Complex SoC Design
GUC works with EDA tool vendors on new automation methodology to improve 60~80% TAT at N5~N12 products successfully.
- Challenge: As computing capability increase a lot in AI/HPC/Networking era, the ASIC design size and complexity grows rapidly. Challenge in P&R productivity by traditional methodology while the number of macros increase to be 10 ~100K times
- Traditional manual and iterative floorplanning process a lengthy part of the implementation schedule
- Traditional macro placement solution is to reduce the cycle-time, but the quality may be not good comparing to manual effort
- Solution & JPR: GUC worked with EDA tools vendors on new automated methodology, and taped out at complex designs successfully
- CDNS: mixed-placer technology
- SNPS: FreeForm Macro Placement technology
- Benefit
- Enhance the floorplan flow and make sure it is smooth for overall flows such as power plan in channel, channel routing, IR and physical verification
- The TAT of floorplanning will be improved from weeks to days and over 10% power and wirelength reduction at N12 Networking project
GUC Core Strengths
- Advanced Packaging Technology Leadership
- Design Engineering Excellence
- Customer Trusted Service