Early Stage IR Drop Prevention: GUC in-house Pseudo CPM (Chip Power Model) for P/G Bump Current Estimation
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Challenge
P/G bump allocation and peak current distribution are critical for IR drop mitigation, especially in power domain edge region.
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Methodology
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Accurately estimate P/G bump peak current in early design stage, based on circuit multi-scenario activity and bump physical location.
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Optimize P/G bump location, circuit design and toggle rate to reduce IR drop issue with customer.
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Benefit
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Enable the quick turn-around time in early design tuning to prevent the localized simultaneous toggle and insufficient bump allocation.
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Serve the efficient DFT circuit topology optimization.
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